ICCCAS 2024 Invited Speaker

Shi-Yu Huang (SMIEEE)

National Tsing Hua University

Biography: Shi-Yu Huang received his B.S. and M.S. degrees from the Electrical Engineering Dept., National Taiwan University, respectively, and his Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara, in 1997. Since 1999, he has joined National Tsing Hua University, Taiwan until now. His recent research is concentrated on all-digital timing circuit designs, such as all-digital phase-locked loop (PLL), all-digital delay-locked loop (DLL), time-to-digital converter (TDC), and their applications to parametric fault testing and reliability enhancement for 3D-ICs. He has published more than 170 technical papers (including 50 IEEE journal papers). Prof. Huang is a senior member.
Speech Title: Jitter Reduction for All-Digital Clock Signal Generation Guided by Jitter Measurement using a Cyclic Time-to-Digital Converter
Abstract: More recently, numerous All-Digital Phase-Locked Loop (ADPLL) or Multi-Phase Delay-Locked Loop (MP-DLL) can be used for on-chip high-speed clock signal generation. For these types of clock signal generators, their key circuit parameters, such as the loop bandwidth in a PLL or the delay of a delay stage in a Multi-Phase DLL can be controlled much more easily than their analog counterparts. This feature makes a jitter learning and optimization process possible in which the clock jitter is reduced by fine-tuning the parameters in a clock signal generator based on the guidance provided by the jitter measurement results. In the first half of this talk, we introduce a process-resilient Cyclic Time-to-Digital Converter (Cyclic TDC) using a technique called One-Way Varactor Cell (OWVC). With this Cyclic TDC, the peak-to-peak jitter of a clock signal can be measured reliably even under process variation. In the second half, we describe how the jitter measurement results can be fed back to a clock signal generator circuit to achieve jitter reduction.